Ceramic pin grid array (PGA) type packages are used to a large extent for many very-large-scale integration (VLSI) devices. The pinned ceramic substrates are typically manufactured by attaching the electrically conductive pins, such as the copper or copper gold-coated pins to the ceramic by means of swaging or impact pinning. Both of these methods (swaging and impact pinning) form the pin heads and bulges that sandwich the ceramic substrate therebetween. However, the processing places undesirable stress on the ceramic substrate, which can cause cracking and/or breakage of the substrate. Typically, about 5% or more of the substrates are damaged and therefore must be discarded.
Stand-offs to provide free space between the integrated chips on the substrate and the subsequently to be provided cap are provided by swaging the corner pins sideways or reforming certain rows of pins.
In order to locate damaged substrates or out of specification parts from production, it is necessary to employ relatively expensive ultraviolet light inspections on the assembly line.
The present techniques are applied to a minimum pin spacing of 0.070 inches with a pin diameter of 0.016 inches minimum. The manufacturing of smaller pin grid spacing and smaller pin diameter needed to increase I/O pins over a given surface area has not been achieved in pinned ceramic products.